Douglas Yu is a TSMC Vice President and Distinguished Fellow, currently responsible for system integration technology pathfinding. He has led TSMC Cu/Low-K technology development. Doug innovated and established industry first system integration technology platform- TSMC 3DFabric^TM, including CoWoS^®, InFO and SoIC^TM. 3DFabric^TM plays critical enabling role in advanced smart devices, and high-performance-compute (HPC) including AI/ML/GAI. It has become an integral part of SoC- and System-scaling. TSMC COUPE^TM, his more recent innovation on Silicon-Photonics integration further enhances system energy-efficiency and performance.

Before joining TSMC, Doug worked with AT&T Bell Labs on advanced SoC technology. He earned Ph.D. from Geargia Tech. He received IEEE Rao Tummala Award, IEEE EPS Microelectronics Manufacturing Award, and President Science Prize, Taiwan. He is an IEEE Fellow, TSMC Distinguished Fellow, a member of National Academy of Engineering, and an Academician of Academia Sinica. He has given numerous invited/keynote/plenary speeches in international conferences, with 150+ papers and (co)-authored 1500+ US patents to elevate system integration technology profile.

TSMC 3DFabricTM Technology platform including CoWoS®, InFO and SoIC® has been established to enable advanced applications including smart mobile, 5G, HPC, AI/ML and most recent generative AI, which make tremendous impact on out human life. In this paper, I will report recent breakthroughs and new outlook on heterogeneous integration that continue the relentless pursue for better system PPA/V and explore new frontier in post Moore’s Law era.

Madhavan Swaminathan is the Department Head of Electrical Engineering and is the William E. Leonhard Endowed Chair at Penn State University. He also serves as the Director for the Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES), an SRC JUMP 2.0 Center www.chimes.psu.edu. Prior to joining Penn State, he was the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC) – a graduated NSF-Engineering Research Center (ERC), Georgia Tech (GT). Prior to GT, he was with IBM working on packaging for supercomputers. Prof. Swaminathan’s interdisciplinary research on semiconductor packaging and systems integration over the years have resulted in 650+ technical publications, 200+ invited presentations (seminars, keynotes, panels), 3 books, 5 book chapters, 31 patents, 33 best paper and student paper awards, 5 GT awards, 2 start-ups, and several international recognitions with the recent one being the 2024 IEEE Rao R. Tummala Electronics Packaging Award (technical field award) for “contributions to semiconductor packaging and system integration technologies that improve the performance, efficiency, and capabilities of electronic systems”. He is also the founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS). He is a Fellow of IEEE, Fellow of the National Academy of Inventors (NAI), Fellow of Asia-Pacific Artificial Intelligence Association (AAIA), and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society. He received his MS and PhD degrees in Electrical Engineering from Syracuse University, USA.

As we enter the era of Artificial Intelligence (AI), there is a need to combine hardware advances with software efficiencies. The AI hardware platforms are expected to become very complex with the integration of computing, communications, sensing, and other capabilities, fueling the need for Heterogeneous Integration (HI). But what are the challenges and what is the future for HI? Why is this important to the EMC community? This presentation will discuss details with a focus on signaling, power delivery, and advanced communication – aspects of HI where the EMC community can have a major impact.

Dr. C.P. Hung currently holds the position of Vice President, Corporate R&D, at ASE Group. Based in Taiwan, he leads teams responsible for next-generation product development featuring integrated technologies, as well as a broad range of advanced chip, package, and system integration solutions with multiple ASE and USI Sites.

During his tenure, Dr. Hung has performed a variety of management roles at ASE, including VP of Corporate Design, VP of Central Engineering & Business Development and VP of Logistic Services Integration. He holds 282 patents encompassing IC packaging structure, process, substrate and characterization technology. He has also published over 129 conference and journal papers.

Dr. Hung has being the SEMICON Taiwan PKG & TEST Committee Chair since 2013, and currently Co-Chair since 2021. He is also a board of governor of IEEE EPS since 2019.

Advanced IC Packages are typically Ball Grid Array (BGA) and Flip-Chip (FC) based with various structures to meet demanding high performance chiplet computing needs. This presentation will discuss innovative BGA, Fan-Out with FC technologies – FOCoS, plus 2.5D / 3D packages, describing how the integration needs are optimized with higher precision, effective layout with enhanced electrical signal and power performance, very essential for new generation AI server, data center, 5G and latest edge computing applications.

Christian Schuster received the Diploma degree in physics from the University of Konstanz, Germany, in 1996, and the Ph. D. degree in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, in 2000. Since 2006 he is full professor and head of the Institut für Theoretische Elektrotechnik at the Hamburg University of Technology (TUHH), Germany. Prior to that he was with the IBM T. J. Watson Research Center, Yorktown Heights, NY, where he was involved in high-speed optoelectronic package and backplane interconnect modeling and signal integrity design for new server generations. His interests include signal and power integrity of digital systems, multiport measurement and calibration techniques, and development of physics-based as well as data-based simulation methods for electromagnetic compatibility and interference problems.

Dr. Schuster received several IEEE Transactions and DesignCon Paper Awards for his contributions to modeling for signal and power integrity. While at IBM, he received several IBM Research Division Awards for his contributions to packaging of high-end server systems. He is a member of the German Physical Society (DPG) and a Fellow of the Institute of Electrical and Electronics Engineers (IEEE). In the past, he was serving as Distinguished Lecturer for the IEEE EMC Society, as Chair of the German IEEE EMC Chapter, as a member of the Board of the EMC Society, as Associate Editor for the IEEE Transactions on EMC as well as an Adjunct Associate Professor at the School of Electrical and Computer Engineering of the Georgia Institute of Technology. Currently, he is serving as President of the NIT Northern Institute of Technology Management (NIT) at TUHH.

In January IEEE Spectrum published its 2025 Tech Impact Study with the headline: “For the second year in a row, top tech leaders selected artificial intelligence as the most important current technology” – truly outstanding … but really surprising!? Since ChatGPT-3.5 was released in November of 2022 hardly a month passes by without news of a novel online tool based on AI or an announcement of a multi-billion dollar investment in an AI related company or data center.

What does all that mean for EMC engineering, i.e. what are the implications for how we design, test, debug, and optimize to achieve Electromagnetic Compatibility, Signal Integrity, and Power Integrity for electronic components and systems? Listening to industry you will hear that AI is already a key element of product design … but how exactly?
In this keynote contribution to the APEMC Conference I will summarize what answers we at Hamburg University of Technology (TUHH) – together with partners – have found to these questions over the past few years. The contribution will focus on the “modeling” part of EMC engineering, i.e. the generation and usage of models to understand, predict, and mitigate EMC-related phenomena. For this I will contrast the usual “physics-based” approach with the new “data-based” or “AI-based” approach and draw conclusions from that. The keynote will close with an outlook to the new European Doctoral Network PATTERN (Enabling Artificial Intelligence for Electromagnetic Compatibility).

[This text was not generated with the help of AI!]

Prabhakar H. Pathak received his Ph.D. (1973) from The Ohio State Univ.( OSU), in the Dept. of ECE where he later joined the faculty and became a Professor. Currently, he is Prof. Emeritus at OSU. He also served as an Adjunct Prof. at the Univ. of South Florida. He is regarded as a co-developer of the Uniform Geometrical Theory of Diffraction (UTD). His interests are in the development of Ray, Wave, and Beam optical methods in frequency and time domains, for solving electrically large Electromagnetic(EM) antenna and scattering problems of engineering interest. He has also developed some Hybrid methods, which combine the best features of any of the above methods with numerical methods, to solve EM problems which cannot otherwise be solved in a tractable fashion by any of the methods when used alone. His work is applicable, e.g., to the prediction of EM radiation and coupling associated with small antennas, or large phased array antennas, placed on or near large structures (such as airborne, spaceborne or naval platforms, etc.) as well as to the EM scattering by such structures. He has presented many invited lectures/short courses in the USA and abroad; also he has published 7 book chapters and several journal and conference papers. He also published a book on EM waves entitled: Electromagnetic Radiation, Scattering, and Diffraction (authors: P.H. Pathak & R.J. Burkholder). He was an Assoc. Ed. for IEEE Trans. AP; an IEEE AP distinguished lecturer (DL) during 1991-1993; chair of the IEEE AP DL program (1995-2005); member of IEEE AP-S AdCom (2010). He received the 1995 IEEE AP Schelkunoff best paper award, the 1996 George Sinclair Award from the OSU ElectroScience Lab, the 2009 ISAP best paper award, the IEEE 3rd Millenium Medal from AP-S, and the 2013 IEEE AP-S Distinguished Achievement Award. He is a Life Fellow of IEEE and member of URSI Commision B.

Some of the major steps in the evolution of ray concepts and methods from about 700 B.C. to the present are briefly reviewed. Starting with the early lens making and theories of light, science of optics began to evolve and came up with the invention of the pin hole camera, the laws of reflection and refraction of light, an explanation for the formation of the rainbow, and conjectures on the finite speed of light. Later the corpuscular theory of light was introduced, but failed to explain the bending of light. it was then replaced by an early ray theory of diffraction but that failed to accurately reproduce the results of the famous double slit diffraction experiment. The latter was thus replaced by an early wave theory of light which was somewhat more accurate. In the 1800s, electromagnetic (EM) waves and light was established to be the same phenomenon. Also the speed of light was later measured and found to be the same as that predicted theoretically by equations governing EM wave propagation. Several other studies subsequently led to a significant ray theory of diffraction where diffracted ray fields existed in addition to reflected and refracted rays. The modern versions of the latter constitute the geometrical theory of diffraction (GTD) introduced in the 1950s and its uniform versions; one such being the uniform theory of diffraction (UTD) developed in the late 1970s, which still continues to be generalized for treating a wide variety of practical EM antenna and scattering problems at moderate to high frequencies.